Programmable logic devices (PLDs) may be configured to perform a variety of functions. A PLD may be programmed with configuration data to configure the logic and routing resources of the PLD to perform a selected function. In certain PLDs, following each power-up of the power supply, a programming time interval is required to load the configuration data into the logic and routing resources of the PLD. The PLD is not ready to perform the configured function until the completion of the programming time interval.
The flexibility of PLDs has lead to widespread use in the electronics industry. However, the programming time interval of a PLD may limit the usage of the PLD in certain applications. For example, a low power application may power-down devices between tasks to conserve power and thereafter require immediate processing when a new task becomes available. However, a PLD may be unsuitable as a device in a low power application if the programming time interval is greater than the required power-up response time of an application.
The present invention may address one or more of the above issues.